Date: April 10, 2024, 4–5:30 p.m. CET.

Speaker: Dr. Andreas Herten (Forschungszentrum Jülich), ORCID

Location:

     Weyertal 86–90, 50931 Cologne
     Mathematical Institute (Google Maps, OpenStreetMap)
     Seminar Room 1 (Room 0.05)

Title: The JUPITER System: Design and Enablement

Abstract: At the end of 2023, the contract was signed for the installation of JUPITER, the first Exascale supercomputer in Europe. The system will consist of a Booster module, with 24 000 NVIDIA GPUs, and a Cluster module, deploying the European SiPearl Rhea Arm CPU. JUPITER is procured by EuroHPC JU together with Germany (BMBF/MKW-NRW) and hosted at Jülich Supercomputing Centre in a modular data-center. The preparative construction is already ongoing, and the installation of the system is starting soon.
The talk will present the JUPITER system design, insights into the procurement process, plans for user enablement, and some very first results of prototype nodes.

Date: January 10, 2024, 4–5:30 p.m. CET.

Speaker: Dr. Tim Gerrits (RWTH Aachen University), ORCID

Location:

     Weyertal 86–90, 50931 Cologne
     Mathematical Institute (Google Maps, OpenStreetMap)
     Seminar Room 1 (Room 0.05)

Title: Bringing Visualization to National HPC Infrastructure: Designing Dialogues

Abstract: The rapid advancements of high performance computing hardware and efficient algorithms allows domain scientists to create more efficient, accurate, and reliable models of real-world phenomena. However, this also leads to an increase of size and complexity of data, resulting in cumbersome or unfeasible analysis processes. While the visualization community has been actively exploring new approaches and metaphors to address these challenges, modern scientific visualization tools have not yet found their way into the day-to-day workflow of domain scientists. As part of the national high performance computing initiative (NHR), the Cross-Sectional Group Visualization aims to bridge this gap.

This talk focuses on the challenges, limitations, and potential of this journey. It covers insights into current practices, wishes, and requirements of HPC users in regards to visualization, gained from the unique network and close collaboration of HPC-related researchers. It presents custom solutions to individual problems and proposes an outlook on the future of visualization within high performance computing.

Date: December 20, 2023, 4–5:30 p.m. CET.

Speaker: Prof. Dr. Matthias Müller (RWTH Aachen University), ORCID

Location:

     Weyertal 86–90, 50931 Cologne
     Mathematical Institute (Google Maps, OpenStreetMap)
     Seminar Room 1 (Room 0.05)

Title: National High-Performance Computing in Germany: NHR and NHR4CES

Abstract: The NHR Alliance (https://www.nhr-verein.de/) pools the resources and expertise of high-performance computing at universities and makes them available to scientists at German universities free of charge. The NHR Alliance does not only provide computing capacity, but also supports users, in particular by providing advice and training in the use of high-performance computing in their fields of application. The services offered by the national network cover a large range of topics and are accessible nationwide. NHR is jointly financed by the federal and state governments. This talk provides an overview of this funding instrument – launched in 2021 – and the nine funded NHR centers. The second part of the talk focuses on NHR4CES (https://www.nhr4ces.de/), the NHR center for Computational Engineering Science, jointly operated by RWTH Aachen University and TU Darmstadt.

Date: November 29, 2023, 4–5:30 p.m. CET.

Speaker: Jens Henrik Göbbert (Forschungszentrum Jülich), ORCID

Location:

     Weyertal 86–90, 50931 Cologne
     Mathematical Institute (Google Maps, OpenStreetMap)
     Seminar Room 1 (Room 0.05)

Title: JupyterLab – How JSC Enables Supercomputing in the Browser

Abstract: Interactive exploration and analysis of large amounts of data from scientific simulations, in-situ visualization and application control are convincing scenarios for explorative sciences. Based on the open source software Jupyter or JupyterLab, a way has been available for some time now that combines interactive with reproducible computing while at the same time meeting the challenges of support for the wide range of different software workflows. Even on supercomputers, the method enables the creation of documents that combine live code with narrative text, mathematical equations, visualizations, interactive controls, and other extensive output. However, a number of challenges must be mastered in order to make existing workflows ready for interactive high-performance computing. With so many possibilities, it's easy to lose sight of the big picture.

Date: November 08, 2023, 4–5:30 p.m. CET. Coffee and tea from 4–4:30 p.m.

Speaker: Viktor Achter (IT Center Cologne / RRZK)

Location:

     Weyertal 86–90, 50931 Cologne
     Mathematical Institute (Google Maps, OpenStreetMap)
     Seminar Room 1 (Room 0.05)

Title: From CHEOPS to RAMSES – The new HPC System at the UoC

Abstract: The RRZK has a long standing tradition of providing infrastructure for scientists as a basis for scientific computing and High Performance Computing.

In this talk, the learnings from the operation of the supercomputer CHEOPS are presented, as well as the design decisions on which the next Tier-2 supercomputer RAMSES ist based on. Furthermore, the current status of the construction and first impressions of the system will be shown.

Date: June 21, 2023, 4–5:30 p.m. CET. Coffee and tea from 4–4:30 p.m.

Speaker: Christie Alappat (Erlangen National High Performance Computing Center), ORCID

Location:

     Weyertal 86–90, 50931 Cologne
     Mathematical Institute (Google Maps, OpenStreetMap)
     Seminar Room 1 (Room 0.05)

Title: Accelerating sparse iterative solvers using Recursive Algebraic Coloring Engine

Abstract: Sparse linear iterative solvers are essential for large-scale simulations. Often in many of these simulations, the majority of the time is spent in matrix power kernels (MPK), which compute the product between a power of a sparse matrix A and a dense vector x, i.e., A^p x. Current state-of-the-art implementations perform MPK by  calling repeated back-to-back sparse matrix-vector multiplications (SpMV), which requires to stream the large A matrix from the main memory p times. Using RACE, we can accelerate the MPK computations by keeping parts of the matrix A in cache for successive SpMV calls. RACE uses a level-based approach to achieve this: Levels are constructed using breadth-first search on the graph related to the underlying sparse matrix. These levels are then used to implement cache blocking of the matrix elements for high spatial and temporal reuse. The approach is highly efficient and achieves performance levels of 50–100 GF/s on a single modern Intel or AMD multicore chip, providing speedups of typically 2x – 4x compared to a highly optimized classical SpMV implementation.

After demonstrating RACE’s cache blocking approach, the talk sheds light on the application of the cache-blocked MPK kernels in iterative solvers. We discuss the benefit of integrating RACE library to Trilinos framework and demonstrate the speedups achieved in communication-avoiding s-step Krylov solvers, polynomial preconditioners, and algebraic multigrid (AMG) preconditioners. The talk concludes by showcasing the application of RACE-accelerated solvers in a real-world wind turbine simulation (Nalu-Wind) and highlights the new possibilities and perspectives opened up by RACE’s cache blocking technique.

Date: June 14, 2023, 4–5:30 p.m. CET. Coffee and tea from 4–4:30 p.m.

Speaker: Dr. Robert Speck (Forschungszentrum Jülich)

Location:

     Weyertal 86–90, 50931 Cologne
     Mathematical Institute (Google Maps, OpenStreetMap)
     Seminar Room 1 (Room 0.05)

Title: Parallel-in-Time Collocation Methods

Abstract: The efficient use of modern supercomputers has become one of the key challenges in computational science. For the numerical solution of time-dependent processes, time-parallel methods have opened new ways to overcome both strong and weak scaling limits. If higher order accuracy in time is feasible, parallelization techniques based on collocation methods can provide temporal parallelism within a single time-step as well as across multiple ones. In this talk, we give an overview of three different approaches to introduce parallel-in-time integration for collocation methods: (1) parallel preconditioners for spectral deferred corrections, (2) the parallel full approximation scheme in space and time, and (3) diagonalization-based preconditioning for multi-step collocation problems. Those approaches can even be combined to obtain multi-time-parallel integrators. We shed light on the pros and cons of the different variants and their implementation on HPC systems. We also discuss current roadblocks and further research directions.

Date: May 10, 2023, 4–5:30 p.m. CET. Coffee and tea from 4–4:30 p.m.

Speaker: Pierre-Edouard Beaucamps (System Application Manager, Kalray)

Location:

     Weyertal 86–90, 50931 Cologne
     Mathematical Institute (Google Maps, OpenStreetMap)
     Seminar Room 1 (Room 0.05)

Title: Introducing Kalray DPU — A Manycore Processor Designed for Performance & Flexibility

Abstract:

The world is facing an explosion of data, bringing new processing challenges. Every day, new algorithms are developed and run on high-performance processors to sustain the computational requirements, which often means going with GPUs.

But technologies developed decades ago, are not always able to handle these massive workloads efficiently, especially in terms of real-time processing, power consumption, heterogeneous multiprocessing, or freedom-from-interference.

Although originally designed for graphics processing, GPUs are indeed very effective at providing high-level computing capabilities, but their architecture can also prevent applications from taking full advantage of their capabilities.

This presentation will introduce a new type of processor designed by Kalray, the MPPA® DPU (Data Processing Unit), based on a unique manycore architecture.

Kalray DPU is a high-performance, low-power programmable processor, capable of competing with GPUs, DSPs, and FPGAs, offering a high level of performance at a competitive cost, and beyond that, one of the best performance per watt ratio available in the market.

Based on the lessons learned from the past, current developments and promises are evaluated in order to derive an outlook, where the implementation of DPUs provides comprehensive advantages in the education and research environment. We will provide a deeper insight, which applications will benefit from DPUs and how a collaboration between University of Cologne and Kalray could look like.

Date: January 25, 2023, 4–5:30 p.m. CET. Coffee and tea from 4–4:30 p.m.

Speaker: Dr. Karl Rupp (TU Wien), ORCID

Location:

     Weyertal 121, 50931 Cologne
     RRZK building (Google Maps, OpenStreetMap), Entrance
     Room 1.03

Title: 15 Years of GPUs for Computational Science: Past, Present and Future

Abstract: General purpose computations on Graphics Processing Units (GPUs) have become widely available with the first release of the CUDA toolkit in summer 2007. In the 15 years that have followed, GPUs have become widely adopted for many general purpose computations in computational science. And yet, there is still an ongoing debate whether “GPUs are worth it” from a productivity point of view. This talk revisits various technological developments in the GPU landscape over these 15 years and discusses current GPU functionality available in popular software libraries such as PETSc. Based on the lessons learned from the past, current developments and promises are evaluated in order to derive an outlook on where computational science using GPUs is headed.

Date: January 23, 2023, 4–5:30 p.m. CET (talk from about 4–5 p.m., followed by a discussion).

Speaker: Dr.-Ing. Michael Klemm (Principal Member of Technical Staff, HPC Center of Excellence, AMD), ORCID

Location:

     Weyertal 121, 50931 Cologne
     RRZK building (Google Maps, OpenStreetMap), Entrance
     Room 1.03

Title: AMD EPYC Processors and Instinct Accelerators — The Journey to Exascale and Beyond

Abstract: High Performance Computing (HPC) is a prevalent and widespread tool to solve advanced, scientific and commercial problems.  Simulating the structure of molecules, computational fluid dynamics, quantum chemistry, or astrophysics are just a few examples of the many domains that employ HPC systems at all scales to solve every-day and not so every-day problems.  AMD has a rich history of providing hardware that helps satisfy the computational demands of today's HPC workloads.  In this presentation, we will recap the developments and innovations at AMD in the recent past and how they led to the current design of AMD EPYC Processors and AMD Instinct Accelerators.  Hardware and software are equally important, and so we will spend a bit of time also on software implications.  We will close the talk with an outlook on what will be coming in the near-term future.

Date: January 18, 2023, 4–5:30 p.m. CET. Coffee and tea from 4–4:30 p.m.

Speaker: Dr. Alexander Heinlein (Delft University of Technology), ORCID

Location:

     Weyertal 121, 50931 Cologne
     RRZK building (Google Maps, OpenStreetMap), Entrance
     Room 1.03

Title: Fast and Robust Overlapping Schwarz Preconditioners in Trilinos — Highly Scalable Algorithms and Their Efficient Implementation

Abstract: The Trilinos library is an object-oriented software framework for the solution of large-scale, complex multi-physics engineering and scientific problems on new and emerging high-performance computing (HPC) architectures. It provides a collection of interoperable software packages enabling the development of algorithms reaching parallel scalability up to the largest supercomputers available.

This talk will discuss different aspects of Trilinos for the example of the FROSch (Fast and Robust Overlapping Schwarz) preconditioning framework, which is part of the Trilinos package ShyLU. FROSch implements multilevel Schwarz preconditioners, which are algebraic, i.e., which can be constructed using only the fully assembled parallel distributed system matrix. Making use of the software infrastructure of Trilinos, FROSch allows for the parallel solution of extremely large problems. Numerical results for various problems indicating parallel scalability up to more than 200,000 MPI ranks will be presented. Moreover, node-level parallelization on CPUs as well as GPUs using the Kokkos programming model through the Tpetra linear algebra framework will be discussed.

Date: December 7, 2022, 4–5:30 p.m. CET. Coffee and tea from 4–4:30 p.m.

Speaker: Prof. Dr. Martin Kronbichler (University of Augsburg), ORCID

Location:

     Weyertal 121, 50931 Cologne
     RRZK building (Google Maps, OpenStreetMap), Entrance
     Room 1.03

Title: Efficient Implementations of High-Order Finite-Element Methods

Abstract: The talk focuses on the efficient implementation of high-order methods in the context of continuous and discontinuous finite elements applied to linear and nonlinear partial differential equations on complex geometries. The core algorithmic ingredient is the matrix-free operator evaluation (matrix-vector product), for which fast quadrature schemes for cell and face integrals based on a technique called sum factorization are employed. The algorithm selection for achieving a high throughput is demonstrated, guided by performance analysis, as well as the scalability to large-scale parallel machines. The best algorithms come with an arithmetic intensity of one to five flop/byte, with memory transfer primarily due to the access into input and output vectors as well as some geometry or variable coefficient data. As a result of our optimizations, many downstream solvers, such as explicit time stepping, smoothers in multigrid methods, or conjugate gradient solvers, are now no longer dominated by the matrix-vector product but by vector operations instead. To overcome this limitation, we consider the whole solution chain and fuse the memory access between different stages of an algorithm. The effect of these optimizations on the performance on contemporary CPU and GPU architectures are illustrated and results are shown of fluid dynamics simulations implemented with computational kernels from the deal.II finite element library.